The present invention concerns a system for controlling Attack-Decay Sustain-Release (ADSR) data output of an electronic musical instrument, and more particularly, a system for controlling the ADSR data output when the keyboard becomes into the off state during the attack data outputting.
Conventionally, an electronic musical instrument has a memory storing the ADSR data for controlling the tone envelope, which ADSR data are controlled to be outputted according to the on and off states of the keyboard of the electronic musical instrument. Such a system of prior art, as shown in FIG. 1, comprises a counter 100 for counting inputted clock pulses CK to output the address data, a memory 200 for storing the address data outputted from said counter 100 to output the ADSR data, a clock pulse controller 300 for receiving a clock pulse CK, the address data of said counter 100 and the keyboard signal, and a latch 400 for latching the output data of said memory 200, said latch being enabled by first control signal of said clock controller 300, said clock controller 300 receiving the keyboard signal Q to supply a reset signal to said counter 100 and then a clock pulse CK thereto, said clock controller cutting off said clock pulse CK to said counter 100 and outputting said first control signal when said counter 100 counts a fixed number of said clock pulses CK, while inputting said clock pulse CK into said counter 100 when said keyboard signal Q is cut off. FIG. 2A illustrates waveforms of the ADSR data output in FIG. 1, wherein FIG. A illustrates the state of the envelope data stored into the memory 200, the data included in the addresses 00-7F in hexadecimal code being the attack data while the data in the addresses 80-FF being the release data, FIG. 2B illustrates the ADSR data outputted from the memory 200 when the keyboard is put on prolonged time maintaining 7F address data waveform, and FIG. 2C illustrates the waveform of the ADSR output when the keyboard is put off in the attack time. In the drawings, the longitudinal axis represents the data level, and the horizontal axis the address concerning time. The reference numeral 11 represents the attack address region, and 13 the release address region. The numeral 12 represents the sustain region, and the numerals 20 and 22 the release data curves. The numeral 20 represents the curve that must be outputted when the keyboard signal Q becomes low during outputting of the attack data.
The operation of the circuit in FIG. 1 will be explained with reference to the waveforms of FIG. 2. During the clock pulse CK being inputted into the clock controller 300, if the keyboard signal Q is inputted as high level, the clock controller 300 supplies a reset signal R to the counter 100 to reset the counter, and outputs the clock pulse CK and the first control signal. Hence, the counter 100 counts the clock pulse CK, inputting the resultant into the memory 200 and the clock controller 300. The memory accesses the data in the location addressed by the output data of the counter 100 to input the envelope data into the latch 400.
In this case, the counter 100 counts the clock pulse from the address 00, while the memory 200 accesses the data according to the address inputted from 00 of the envelope data as shown in FIG. 2A. When the counter 100 outputs the address data within 7F, the memory 200 delivers to the latch 400 the envelope data in the address corresponding to the portion 11 in FIG. 2A. The latch 400 is operated by the first control signal of the clock controller 300 to buffer the envelope data, outputting them through the output line 500. The clock controller 300 receiving the counted data of the counter 100, i.e., the address data of the memory 200, cuts off the clock pulse CK to stop the data access of the memory 200 if the counted data is half 7F the full address FF. Therefore, since the final input data of the latch 400 are outputted through the output line 500, the sustain data are obtained as shown in the portion 12 in FIG. 2B.
During the sustain data being outputted as above, if the keyboard signal becomes low, the clock controller 300 delivers only a fixed number of the clock pulses CK to the counter 100. Hence, the counter 100 sequentially counts the output data of 7F counting as in the series 80, 81 . . . , thereby inputting the address data signals into the memory 200 and the clock controller 300. The memory 200 receiving the data outputted from the counter 100 outputs the release data of the address 80-FF as shown by the portion 13 in FIG. 2A immediately after the sustain portion 12 in FIG. 2B. If due to the clock pulse outputted from the clock controller 300 are outputted the release data (the portion 13 in FIG. 2A) stored into the memory 200, the ADSR data are outputted from the latch as shown in FIG. 2B.
On the other hand, the clock controller 300 receiving the output data of the counter 100 as the address of the memory 200 resets the counter 100 and cuts off the clock pulse CK to stop the output of the ADSR data if the input address becomes the signal indicating the full address FF of the memory 200. In such a system of prior art, while the foregoing operation makes the counter 100 to count the data up to the half address 7F of the full address FF in the active high of the keyboard signal Q as shown FIG. 2C, if the keyboard signal Q becomes low, the counter 100 continuously counts the inputted clock pulses CK from the start address 00 to the full address FF, so that the ADSR waveform which must be outputted as shown by the portion 20 in FIG. 2C is outputted as shown by the portion 22 in FIG. 2C. Consequently, the ADSR waveform of the tone of the electronic musical instrument is not correctly outputted according to the state of touching the keyboard so that the tone quality of the electronic musical instrument is deteriorated.